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  • INTEL-Stratix


【INTEL-Stratix FPGA】 devices address the design challenges of next-generation high-performance systems across wired and wireless communications, computing, storage, military, broadcast, medical, and test and measurement end markets.
    Intel® Stratix® 10 FPGA Features and Benefits
    Up to Twice the Core Performance
    The breakthrough Intel® Hyperflex™ FPGA architecture boosts core performance by up to 2x.1 With the Intel® Stratix® 10 product family, you can take performance to the next level, achieving up to 8.6 TFLOPS of single-precision floating-point DSP performance and up to 20 100 GbE interfaces.
    Up to 7x increase in transceiver bandwidth compared to previous-generation FPGAs

    Breaks bandwidth barriers by integrating up to 144 transceivers in a single device with data rates up to 57.8 Gbps PAM-4 and 28.9 Gbps NRZ. 287.5 Gbps DDR4 memory bandwidth. 512 Gbps HBM2 memory bandwidth. 16 GT/s). Intel® Hyperlane Interconnect (Intel® UPI) hardcore IP includes 20 lanes with transfer speeds of 11.2 GT/s to support future specific Intel® Xeon® Scalable processors in a direct cache coherency manner.

    Up to 16 GB of in-package HBM2 memory
    Higher levels of system integration are achieved with the largest single FPGA device with 2.8 million logic elements and a heterogeneous 3D SiP solution that includes transceivers and other advanced components such as HBM2. Additional system support includes standard external memory and Intel® Athon™ memory products. Intel® Stratix® 10 SoC FPGAs feature 64-bit quad-core ARM* Cortex-A53 up to 1.35 GHz, hardened peripherals and a high-bandwidth interface capable of connecting directly to the FPGA fabric at 30 Gbps.

    For high-throughput AI applications up to 143 INT8 TOPS or 286 INT4 TOPS 
    The Intel® Stratix® 10 NX FPGA embeds a new AI-optimized module called the AI Tensor Block, which is tuned for general matrix-matrix multiplication or vector-matrix multiplication used in AI computations, with features designed to work efficiently with small as well as large matrices. A single AI Tensor Block can achieve
    143 INT8 TOPS or 286 INT4 TOPS.

    Intel® Hyperflex™ FPGA Architecture
    To address the challenges of next-generation systems, Intel® Stratix® 10 FPGAs and SoC FPGAs feature a new Intel® Hyperflex™ FPGA architecture that delivers up to 2x higher clock frequency and up to 70% lower power consumption than previous generation high-end FPGAs

    Heterogeneous 3D Integration
    Intel® Stratix® 10 FPGAs and SoC FPGAs use heterogeneous 3D system-in-package (SiP) technology to integrate a single FPGA core fabric and 3D SiP transceiver blocks, along with other advanced components, in a single package.

    Intel® Stratix® 10 FPGAs and SoC FPGAs introduce a new era of transceiver technology with the introduction of innovative heterogeneous 3D system-in-package (SiP) transceivers.

    External Memory Interface
    Intel® Stratix® 10 devices offer memory interface support, including serial, parallel interfaces and specific Intel® Athon™ data center-class persistent memory.

    Artificial Intelligence Tensor Block
    The Intel® Stratix® 10 NX FPGA embeds a new module optimized for artificial intelligence called the AI Tensor Block, which is tuned for general matrix-matrix multiplication or vector-matrix multiplication used in artificial intelligence computations and features designed to work efficiently with small as well as large matrices. A single AI Tensor Block can achieve 15x and more INT82 throughput compared to a standard Intel® Stratix® 10 FPGA DSP module.
    With Intel® Stratix® 10 devices, digital signal processing (DSP) designs can achieve 8.6 trillion floating point operations per second (TFLOPS) in IEEE-754 single precision floating point operations.

    Interconnect with CPUs, ASICs, and ASSPs
    Intel® Stratix® 10 DX devices accelerate applications used in the data center, networking, cloud computing, and test and measurement markets with hard-core and soft-core IP modules that support UPI and PCIe 4.0 interfaces.

    Hard-Core Processor Systems
    Thanks to Intel‘s leadership in SoCs, the next-generation Hard Core Processor System (HPS) for Intel® Stratix® 10 SoC FPGAs delivers the industry‘s highest performance and power-efficient SoCs.

    Benefits of Intel® Stratix® 10 SX SoC FPGAs
    Enables higher levels of system integration
    Intel® Stratix® 10 SoC FPGAs support the USRs in the ARM* ecosystem. ARM‘s next-generation 64-bit architecture (ARMv8) supports hardware virtualization, system management and monitoring capabilities, and accelerated pre-processing. ARM* Cortex-A53* processors support 32-bit execution modes and motherboard support packages for leading operating systems such as Linux*, Wind River VxWorks*, Micrium uC/OS-II* and uC/OS-III*.
    Optimized FPGA and SoC FPGA design software to help designers achieve superior productivity
    A new engine optimized for FPGA designs with millions of logic elements (LEs) significantly reduces the number of design iterations. The Intel® Stratix® 10 SoC FPGA Virtual Platform supports early software development and verification and C-language based design entry using the Intel® FPGA SDK for OpenCL™, providing a design environment that is easy to implement on SoC FPGAs. Heterogeneous debugging, analysis and overall chip visualization are performed with the Intel SoC FPGA Embedded Development Suite (EDS) featuring the ARM* Development Studio 5* (DS-5*) Intel SoC FPGA Edition tool suite.


    ASIC Prototyping
    Reduce design partition complexity and increase efficiency with a single FPGA architecture.

    Network Security
    Over 900 MHz fMAX allows monitoring of all supported protocols at line rate.

    Data Center Acceleration
    UPI, configurable DSP engines, and artificially self-empowered Tensor modules with direct coherent connectivity to select future Intel® Xeon® scalable processors for breakthrough computational throughput.

    Reach fMAX in excess of 700 MHz with Intel® Hyperflex™ FPGA architecture supporting 400G Ethernet.

    Up to 8.6 TFLOPS of IEEE 754-compliant single-precision floating-point performance, supporting GPU-level performance at extremely low power consumption.

    OTN/Data Center Interconnect
    Heterogeneous 3D system-in-package (SiP) transceiver block integration provides 30G backplane support and transitions to 57.8 Gbps and 28.9 Gbps.
    Please submit your basic information, we will contact you as soon as possible!





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